Brazilian, born May 5th, 1985.
Flat B, 33 Great James Street, WC1N 3HBLondon, UK.
Phone: +353(0)863413583 — Email:


Feb 2015 - Present

Senior R&D software engineer, Bloomberg LP, London, UK.
Working in the Shared Services (middleware API) and Audit team for AIM/Trading Systems. We build a framework for consolidated data access across multiple data sources and databases for other teams. Agile/Scrum master.

Sep 2011 - Jan 2015 (3 years 5 months)

Senior R&D engineer, Synopsys, Dublin, Ireland.
I worked on PrimeTime, an electronic-circuit static-timing analysis tool that calculates worst-case signal propagation delays and checks timing constraints. PrimeTime is used by semiconductor companies such as Intel, Samsung, AMD and nVidia, to ensure integrity of their designs before signoff for manufacture.
My team was focused on improving the performance and capacity of the tool, keeping it well ahead of Moore’s law -- and of our competitors. As a Senior R&D Engineer, I was tasked with constantly searching for opportunities for performance improvements through profiling and similar techniques. I had an extensive exposure to PrimeTime's very large C++ code-base and as a result I directly proposed and followed multiple projects from idea to completion. These projects included multi-threading, low-level optimisations to our memory allocators, deployment of inlining and algorithmic enhancements to various areas.
My most significant projects were: optimizing the netlist in-memory representation, redesigning and rewriting a multi-threaded collection search and matching engine, and adding a parallel foreach (interprocess map-reduce) built-in command to a Tcl interpreter.
I had a central role as a reference in C++ within the team. During our product-wide migration from C to C++, I was trusted as a local contact in the refreshing of our coding guidelines. I gave talks on C++ topics to the rest of the team. I also took part in interviews and ramp-up of new hires.

May 2008 - May 2011 (3 years)

R&D engineer (part-time during my Ph.D), STMicroelectronics, Grenoble, France.
I worked on transactional-level modelling, a technique for early architecture exploration and simulation of embedded systems. I wrote and analysed complex multi-threaded code in C++ and Java. I directly supervised three Master-level students during their 6-month, last-year projects.

Nov 2007 - Apr 2008 (6 months)

Research engineer, Joseph Fourier University, Grenoble, France.

Oct 2006 - Jun 2007 (9 months)

Research intern, Verimag Research Lab, Gières, France.

Feb 2006 - Aug 2006 (7 months)

Engineering intern, STMicroelectronics, Grenoble, France.
I performed integration of different components in a SystemC model of the STn8815 Nomadik Multimedia Processor, then ported the whole platform from Solaris to Linux.

Nov 2003 - Aug 2005 (1 year 10 months)

Undergraduate assistant, Embedded Systems Lab, Porto Alegre, Brazil.
SystemC, Verilog, embedded C, Linux



Ph.D, Computer Science, Grenoble University, France.


Double degree, with honors
M.Sc, Computer Science, Joseph Fourier University, France.
M.Eng, Telecommunications, ENSIMAG, Grenoble Institute of Technology, France.


B.Eng, Computer Engineering, Federal University of Rio Grande do Sul, Brazil.



I am dynamic, curious and fast learning. I like challenges, team working and sharing knowledge. I have experience talking in conferences and seminars. I have taught several subjects at university, including object-oriented programming, Java, C and computer architecture. I speak fluent English, French and Portuguese.


My expertise and communication skills usually make me the go-to person for C/C++ questions around the workplace. I have contributed patches to open-source projects such as GCC, Git and Inkscape. I have some experience in multi-threading and optimization. I am also proficient in shell scripting and Python.


Skiing, hiking, via ferrata, playing the piano.